In modern computer and digital processing technology, there is a continual demand for increases in system performance. Increased system performance may be obtained by increased switching speeds, faster clocking rates and higher computational capacities, among other things. Increases in system performance are also realized by greater component packaging and assembly densities and shorter signal conductive paths. Greater densities and shorter conductive paths reduce the length of the paths over which the signals travel and thereby reduce the time consumed in signal propagation between components.
Greater packaging and assembly densities in assembled systems or subsystems increase the inaccessibility of the components for repair or fault testing. Considerable difficulty and expense can be encountered when attempting to locate faulty circuits and components in assembled systems and subsystems. This is particularly the case where systems and subsystems are assembled from non-standard components as opposed to pre-packaged and pre-tested components. As a consequence, tests have been developed for testing the ICs at the die (IC chip) level before the ICs have been cut from the wafer upon which they are fabricated and before the ICs are packaged or assembled into systems or subsystems. Identifying the faulty ICs at the die level saves the expense of packaging the defective ICs and the expense of assembling systems and subsystems from defective ICs. Two basic types of IC tests have been developed to identify faulty ICs at the die level.
One typical IC test is a continuity test wherein electrical signal paths are tested for continuity. Many times, such tests fail to reveal faults or defects which manifest themselves only during operation of the system. Furthermore, continuity tests do not fully test the operational capabilities of the ICs, and those faults which are revealed during functional operation are not usually revealed by continuity tests. However, continuity tests are usually quicker to perform and are performed by lower cost test equipment.
Another type of IC test is a functional test. A functional test assesses the actual operation of the IC in question. Functional tests generally provide a better, more reliable indication of the condition of the IC, than is available from a continuity test. One of the disadvantages of functional tests is that full functional tests may require a considerable amount of time to accomplish the many different permutations of the functional features of an IC. Consequently, only selected functional features are tested while other functional features are not tested. Another concern with functional testers is that their operational speed may not match the functional speed of the IC in the assembled system. For example, the ICs in complex high speed computers may be required to operate or switch at speeds or rates of hundreds of millions of times per second. However at these high switching speeds, most currently available functional test equipment is incapable of supplying reliable signals to the IC and/or is incapable of detecting and measuring the signals delivered from the IC. Degradation in signal integrity and signal propagation occurs at such high speeds during testing but would not occur when the IC is assembled into the overall system where signal integrity and propagation is more controllable. Consequently, most current functional test equipment does not test ICs at their intended operating rate, but instead, tests the ICs at a slower switching speed.
The advent of gallium arsenide (GaAs) semiconductor ICs has dramatically increased the functional speed at which signals can be switched and propagated. Unlike slower speed silicon semiconductors, GaAs ICs commonly exhibit functional failures that appear only at the higher switching or clocking speeds. However at lower speeds, the same GaAs ICs may appear acceptably functional. The functional failures that appear at higher switching speeds are often due to substrate effects that cause duty cycle problems. As a result, low voltage states may not be achieved fast enough for proper functionality at high switching speeds, for example at 500 MHz, even though adequate functionality can be achieved at lower switching speeds, for example at 250 MHz.
Other problems relating to testing GaAs ICs at the chip or die level relate to making adequate electrical contact with the very small contact pads on the die, and maintaining the integrity of the signals applied to and received from the die in order to determine whether it is adequately functional. Much of the signal generation and signal analysis occurs in test system components which are spaced a considerable distance from the die, thereby requiring that the signals obtained from the die be routed efficiently and to avoid or prevent intervening signal degradation.
Thus, there is a unique need for a very high speed functional test system which is capable of detecting IC failures at extremely high switching speeds such as those prevalent in GaAs ICs. Inherent requirements of such a very high speed functional test system are the ability to maintain close control over the propagation of the generated and acquired test signals, and the ability to synchronize the signal generation and acquisition equipment of the test system to measure the necessary timing considerations at the higher speeds and thereby measure the sufficiency of the performance characteristics of the die.